Alexandria Digital Research Library

Integrated CMOS controller for fast optical switching

Chen, Luis
Degree Grantor:
University of California, Santa Barbara. Electrical & Computer Engineering
Degree Supervisor:
Luke Theogarajan
Place of Publication:
[Santa Barbara, Calif.]
University of California, Santa Barbara
Creation Date:
Issued Date:
Physics, Optics, Engineering, Electronics and Electrical, and Engineering, Computer
Optical Switch
Data center switch
Dissertations, Academic and Online resources
Ph.D.--University of California, Santa Barbara, 2013

The growth in data centers traffic today is demanding more energy efficient way of computing and moving data across servers. Recent advances in silicon photonics open up exciting opportunities to solve the bandwidth limitation both on-chip and off-chip wire interconnects. On-chip photonic interconnects have been proposed to link multi-core systems to create a single logical compute node with terascale processing capability in an energy efficient manner. Within the data center, packet switching network is the preferred way of connecting compute servers because of low latency and high network utilization. Optical packet switching becomes an attractive solution as the demand for bandwidth increases. Traditional electronic network switches approach the power consumption limits as data-rates continue to scale higher. While optoelectronic and MEMS optical network switches can be large with hundreds of ports, but they are too slow for packet switching. Furthermore, the high costs and power consumption are barriers to mass commercialization. The key to overcoming this barrier is to integrate both active and passive photonic devices with CMOS and take advantage of the economy of scale of mature silicon manufacturing processes and thus lowering the cost while simultaneously enhancing the reliability of optoelectronic systems.

In this work a fully integrated controller is designed and implemented in a 0.13mum CMOS process. The controller consists of a 2-Channel optical packet header receiver that integrates a novel burst-mode truly differential transimpedance amplifier, limiting amplifier and a burst-mode gated-oscillator based clock and data recovery circuit on the same chip, which also includes an on-chip phased-locked loop to generate the data clock, resulting in an ultra-fast lock time of 13ns, at low power consumption of 43.6mW per channel at 2.5Gbps operation. Second, the design of a low-power, area efficient and adjustable output optical switch fabric driver is presented. The driver enables 3.8ns of switching time when driving a 2x2 optical switch while consuming 150 muW of static power and occupies 0.01mm2 of silicon space. Finally, the design of an automatic power control loop that enables optical gain of up to 12dB is presented. The ability to compensate for optical losses enables the construction of large port count switches that are necessary for data center applications. Optical switching is just one example of electronic-photonic integration. The integration approach can be applied to optical transceivers, optical interconnection of multi-core processors on a supercomputer chip, and many telecom/data-com applications, including Fiber-to-the-Home transceivers, Dense Wavelength Division Multiplex (DWDM) transceivers, and optical Reconfigurable Optical Add-drop Multiplexers (ROADMs).

Physical Description:
1 online resource (144 pages)
UCSB electronic theses and dissertations
Catalog System Number:
Inc.icon only.dark In Copyright
Copyright Holder:
Luis Chen
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