Alexandria Digital Research Library

Improving Non-Volatile Memory Lifetime through Temporal Wear-Limiting

Author:
Neely, Brian Kenneth
Degree Grantor:
University of California, Santa Barbara. Electrical & Computer Engineering
Degree Supervisor:
Frederic Chong
Place of Publication:
[Santa Barbara, Calif.]
Publisher:
University of California, Santa Barbara
Creation Date:
2014
Issued Date:
2014
Topics:
Engineering, Computer and Computer Science
Keywords:
Non-volatile memory
Endurance
Genres:
Dissertations, Academic and Online resources
Dissertation:
M.S.--University of California, Santa Barbara, 2014
Description:

Non-volatile memory technologies provide a low-power, high-density alternative to traditional DRAM main memories, yet all suffer from some degree of limited write endurance. The non-uniformity of write traffic exacerbates this limited endurance, causing write-induced wear to concentrate on a few specific lines. Wear-leveling attempts to mitigate this issue by distributing write-induced wear uniformly across the memory. Orthogonally, wear-limiting attempts to increase memory lifetime by directly reducing wear. In this paper, we present the concept of temporal wear-limiting, in which we exploit the trade-off between write latency and memory lifetime. Using a history of the slack between per-bank write operations, we predict future write latency, allowing for up to a 1.5x memory lifetime improvement. We present two extensions for improving the effectiveness of this history-based mechanism: a method for dynamically determining the optimum history size, and a method for increasing lifetime improvement through address prediction.

Physical Description:
1 online resource (48 pages)
Format:
Text
Collection(s):
UCSB electronic theses and dissertations
ARK:
ark:/48907/f3st7mzv
ISBN:
9781321202663
Catalog System Number:
990045116240203776
Rights:
Inc.icon only.dark In Copyright
Copyright Holder:
Brian Neely
File Description
Access: Public access
Neely_ucsb_0035N_12153.pdf pdf (Portable Document Format)