Alexandria Digital Research Library

Realization and Formal Analysis of Asynchronous Pulse Communication Circuits

Miller, Merritt Philip
Degree Grantor:
University of California, Santa Barbara. Electrical and Computer Engineering
Degree Supervisor:
Forrest D. Brewer
Place of Publication:
[Santa Barbara, Calif.]
University of California, Santa Barbara
Creation Date:
Issued Date:
Engineering, Electronics and Electrical, Engineering, Computer, and Computer Science
Dissertations, Academic and Online resources
Ph.D.--University of California, Santa Barbara, 2015

This work presents an approach to constructing asynchronous pulsed communication circuits. These circuits use small delay elements to introduce a gate level sense of time, removing the need for either a clock or handshaking signal to be part of a high-speed communication link. This construction method allows the creation of links with better than normal jitter tolerance, allowing for simple circuit architectures that can easily be made robust to radiation induced soft error.

A 5Gbps radiation-hardened link, targeted at use in detector modules at the LHC, will be presented. This application presents a special challenge due to both very high radiation levels (1+MGy life time dose) and the demand for minimum resource (area, power, cable cost) use. The presented link, realized in 130nm technology, is unique in that it has low power (~50mW end to end) and very low area 0.12mm2 including electrostatic discharge protection, and I/O amplifiers. Due to its asynchronous construction and the gate design style, the link has essentially zero power dissipation when idle, and enters and exits its idle state with no delay.

In addition to the construction of the link, this presentation covers the design and analysis methodology that can be used to create other asynchronous communication circuits. The methodology achieves higher performance than conventional static technology but needs only a reasonable design effort using tools and strategies that are only mildly extended versions of those familiar to digital static designers. It is used to construct the serializer, deserializer, and self-test circuitry for the presented link. In this case, a 5Gbps SER/DES and a 2GHz parallel pseudo-random number generator are implemented in 130nm CMOS technology using a gate design style that does not dissipate static power.

Physical Description:
1 online resource (153 pages)
UCSB electronic theses and dissertations
Catalog System Number:
Inc.icon only.dark In Copyright
Copyright Holder:
Merritt Miller
File Description
Access: Public access
Miller_ucsb_0035D_12530.pdf pdf (Portable Document Format)