Alexandria Digital Research Library

Interconnect Fabric Reconfigurability for Network on Chip

Author:
Almog, Omri
Degree Grantor:
University of California, Santa Barbara. Electrical & Computer Engineering
Degree Supervisor:
Malgorzata Marek-Sadowska
Place of Publication:
[Santa Barbara, Calif.]
Publisher:
University of California, Santa Barbara
Creation Date:
2015
Issued Date:
2015
Topics:
Electrical engineering and Computer engineering
Keywords:
NoC
VeSFET
SoC
Reconfigurable
Network on Chip
Genres:
Dissertations, Academic and Online resources
Dissertation:
M.S.--University of California, Santa Barbara, 2015
Description:

Microprocessor architectures are evolving at a pace greater than ever before. To meet the industry's stringent power, performance and cost demands there is a rising trend towards building heterogeneous processors with both CPU cores and off-chip components on the same chip. This is known as a System on Chip. These systems show promising solutions including chip interconnects consisting of Network on Chips (NoCs). These NoCs are composed of routers that control traffic, and channels used to connect different components of the chip itself together. Depending on the processor core's type, specifications, and technology used, the NoC fabrics may consume anywhere ranging from 28% to 40% of the total system power.

To reduce this significant power consumption, various solutions were proposed targeting CMOS technology. In this work we focus on NoC topology improvements and reconfigurability using novel VeSFET technology. The work deploys tools used to simulate full systems, such as GPGPUSIM, to evaluate the possible performance/power gains of a hybrid CMOS-VeSFET system. This hybrid system includes CMOS core and memory layers, while the NoC layer is made up of VeSFET transistors. This allows for shorter wire lengths between routers and cores, as well as it permits for extra area to include network reconfigurability features.

The necessary modifications to build this hybrid system are area changes due to VeSFET additional layer, routing length changes, pipelining changes, and VeSFET technology parameter additions. The tools modifications necessary to include this system are described in further details in this thesis. The gathered data indicates great promise for the hybrid reconfigurable CMOS-VeSFET system over the conventional non-reconfigurable CMOS system. It is demonstrated that the hybrid VeSFET system has both a power decrease of approximately 57.0% and a performance increase of approximately 50.2%.

Physical Description:
1 online resource (44 pages)
Format:
Text
Collection(s):
UCSB electronic theses and dissertations
ARK:
ark:/48907/f357196j
ISBN:
9781339083766
Catalog System Number:
990045715340203776
Rights:
Inc.icon only.dark In Copyright
Copyright Holder:
Omri Almog
File Description
Access: Public access
Almog_ucsb_0035N_12591.pdf pdf (Portable Document Format)